-- $Id: $
-- File name:   SHIFT_REG_16.vhd
-- Created:     4/6/2011
-- Author:      Brandon Blaine Gardner
-- Lab Section: 337-06
-- Version:     1.0  Initial Design Entry
-- Description: 16-bit shift register with enable signal.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity SHIFT_REG_16 is
  port
  (
    CLK	         : in  std_logic;
    RST_N        : in  std_logic;
    SHIFT_ENABLE : in  std_logic;
    D_ORIG       : in  std_logic;
    RCV_DATA     : out std_logic_vector(15 downto 0)
  );
end SHIFT_REG_16;

architecture simple_shift_reg of SHIFT_REG_16 is
  signal present_val : std_logic_vector(15 downto 0);
  signal next_val : std_logic_vector(15 downto 0);
  --signal delayD : std_logic;
  
begin
   
  process (CLK, RST_N)
  begin  -- process
    if( RST_N = '0' )
    then
      present_val <= "0000000000000000";
      --delayD <= '0';
    elsif (rising_edge(CLK)) 
    then
      present_val <= next_val;
      --delayD <= D_ORIG;
    end if; 
  end process;
  
  -- Next value logic: Shift in to the right when told to
  next_val <= present_val(14 downto 0) & D_ORIG when (SHIFT_ENABLE = '1') else present_val;
  
  -- Output Logic
  RCV_DATA <= present_val(15 downto 0);
   
end simple_shift_reg;
